Last update: 26th July 2007.
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<<Click here to find out how to build your own ZX80>>
The circuit presented here is designed to be an add-on to the ZX80 circuit described on my ZX80 home page. Adding this to the ZX80 circuit and using the ZX81 ROM will allow you to build a FULLY FUNCTIONING ZX81 USING DISCRETE TTL. This page contains a circuit designed by myself (with a little help from others - Wilf Rigter for details of IN and OUT port numbers and Doug Duchene for providing me with a scan of an old NMI generator which helped me complete my design) along with a circuit description and parts list. The T-state synchroniser part is taken from Sinclair's ZX81 schematic.
To allow the ZX80 circuit to become a fully compatible ZX81, two modifications are required:
1. Replace the 4K ZX80 ROM with an 8K ZX81 ROM.
2. Add some hardware to ensure the screen is properly refreshed during program execution.
In slow mode, the screen is processed as follows:
1. Vertical sync, performed using software.
2. The blank part above the display. The processor is executing the program at
this stage, so additional hardware is used to create the sync signals to keep
the video display locked.
3. The actual screen display. The processor is now back in control of the
display and is used to create the sync signals and the actual character display.
4. The blank part below the display. Again, the additional hardware is switched
back into use to allow the sync signals to be created while the processor
executes the programs.
So, here is a circuit which can be used to create these missing sync signals...
Note: IC U6:B, IC U6:A, D1, R4 and C4 are not needed for converting the ZX80 to a ZX81 but I would recommend doing so to allow the video to be displayed correctly on a TV screen without the need to turn up the brightness. This part of the circuit can also be used without the rest of the NMI hardware on the original ZX80 circuit to improve the ZX80 video.
It is during the blank areas that the programs can run. During these periods the NMI pulses are required to interrupt the processing to generate the HSYNC pulses required for a stable TV display. Once a number of HSYNCS have been generated the NMI generator is turned off and the CPU enters the ROM routine for producing the display. During this time the HSYNCS are produced under software control. At the end of the character display the NMI generator is turned back on and the program in memory can resume running. Again, during this period the program is interrupted by the NMIs to produce the HSYNC pulses. Once a number of pulses have been generated, the NMIs are again turned off and the CPU executes the ROM routine for scanning the keyboard and producing the VSYNC pulse. The above procedure cycles to produce a continuous display.
The circuit can be split into several defined areas:
1. The free-running sync generator, creating a pulse of 20 cycles every 207
cycles. These values are chosen to EXACTLY match the syncs produced by the ZX81
ROM when the character part of the display is being drawn. Any mismatch will
result in the monitor temporarily losing the lock on the SYNC signal, and the
display will slant.
2. The WAIT circuit, to resynchronise the processor to the start of the processor cycle.
3. The NMI on/off latch. The NMI pulses are to be turned on by an OUT FD,A and turned off by an OUT FE,A.
4. The SYNC mixer - here, the software controlled SYNCS are passed through when the NMI is off and the hardware-generated syncs are passed through when the NMI is on. Gating ensures only the correct signals are passed through.
Clock generator
Horizontal pulses during the non-character display part of the TV frame are produced by the NMI generator. As a result, this generator must duplicate the line frequency of the TV signal precisely. The ZX80 produces a pulse lasting 20 clock cycles @ 3.25MHz (giving a duration of 6.15uS). This pulse is produced at 207 clock cycle intervals (giving one pulse every 63.69uS).
However, if this circuit produces 20 cycle pulses at a 207 clock interval, the
top line of characters will slant. The reason behind this is because the ROM
code will start the software generated SYNCs 189 cycles after the fall of the
last hardware generated (ie. NMI) SYNC. This will result (for one line only) in a
sync period of 209 (ie. 189 + 20) cycles. This slight mismatch is enough to make
the TV display lose a tight lock on the synchronisation and the character
display for the next few lines will be at a slant. Even a 1 cycle mismatch
produces a noticeable slant on the screen. To solve this, I have two working
methods...
1. Delay the sync pulse from the hardware by 2 cycles - this I have achieved
using a simple R-C delay, and works well but needs adjustment of the time
constant (preset resistor) to get the alignment correct.
2. The circuit presented here which has a pulse width of 18 cycles. Using this
shorter pulse width, the line period remains exactly 207 cycles throughout the
whole display ie. same for the hardware generation, the transitions and the
software generated part of the screen. The TV is very fussy about the sync
period, but flexible on the sync pulse width, so this minor change to the pulse
width still gives a stable display.
Character line count reset
During the hardware generated video part of the screen, the CPU runs the software. However, this can cause the character line reset to become active at various times so when the characters are then displayed (during the software display part of the screen refresh) the top line of the character is not always zero as it may have been reset at any time during the blank part of the screen. This count is automatically updated for every SYNC pulse and should always be zero when the top line of the character is displayed. The effect of this is that you sometimes get random jumps (actually a roll) in the characters when programs are being executed.
This is solved by disabling the reset circuitry during the NMI-active (ie. hardware generated) parts of the screen.
Feeding the signals through the circuit
While the NMI is ON, the HSYNC signals passed to the video output must be from the NMI generator only as spurious HSYNC signals are produced by the existing circuit. During the character display, the NMI is off so the pulses are obtained from the existing HSYNC circuit.
A small problem exists here. When an OUT FE,A is issued (to turn off the NMI) an additional spurious HSYNC pulse is generated by the ZX80 circuit. This is due to a limitation in the original ZX80 design where IORQ will generate a pulse if the SYNC is currently high. This spurious pulse is masked out by stretching the NMI enabled pulse to cover this glitch, This will prevent a black line appearing just above the top character on the TV display (and the character line count being incorrectly incremented).
Power-up reset
No resetting of the flip-flops is required since the first instruction issued by the ZX81 ROM is an OUT FE,A (turn off NMI).
A little note about the video
The CCIR definition for a 625 line video signal includes the following...
Each line has a 64uS duration,
giving a line frequency of 15.625kHz.
The blanking part of the line signal should be 12uS long, consisting of:
1.5uS front porch
4.7uS horizontal sync
5.8uS back porch
Needless to say, the ZX80 and ZX81's are a
bit off on ALL timings!
ie.
1 line is 207 cycles, giving a 63.69uS duration (15.701kHz
frequency)
For the ZX80, each sync is 20 cycles long, giving a duration of 6.15uS
For the ZX81, each sync is 16 cycles long, giving a duration
of 4.9uS (much closer than the ZX80)
There is no front porch (not important)
There is no back porch (except on the latest issue of the
ZX81)
The back-porch is an important part of the video signal which is used (among others) to set the black-level of the video signal. When a "black on white" display is being displayed, the lack of this being correctly set results in the whole display being dark, which is why you need to turn the brightness up. When using "white on black", the start of the line is dark, so the video is correctly displayed with the dark level being correctly sampled. This can be easily cured, and is shown on the bottom-right of the circuit.
This circuit is incorporated into the existing ZX80 circuit as follows (bold letters refer to my circuit, any other numbers refer to the original ZX80 circuit):
The WAIT, HALT, NMI, A0 and A1 signals are taken to the Z80 CPU.
The /PHI is taken from IC18 pin 8 or 12
The connection between IC19 pin 8 and IC 21 pin 1 / R32 is to be broken.
SYNC IN is connected to IC19 pin 5
SYNC OUT is connected to IC21 pin 1 / R32.
IORQ+WR is connected to IC17 pin 6
The connection between IC21 pins 2/3 and IC 11 pins 10/11 needs to be broken.
RST IN is taken from IC11 pin 10/11
RST OUT is taken to IC21 pins 2 and 3
The connection from the video out
to the modulator (between IC9 and R30) is to be broken.
VIDEO IN is taken from IC9 pin 7 or 9
VIDEO OUT to R30
The 8K ZX81 ROM is required for SLOW-mode to work. NMIs will not work with the ZX80 ROM - it will cause the ZX80 to crash. The 8K ROM requires A12 from the Z80 to be taken to A12 on the ROM. /OE on the ROM is to be permanently grounded.
My other pages
Build your
own ZX80 - my page showing
you how to build this old micro
|__
ZX80 to
ZX81 conversion - build the NMI generator needed to convert the ZX80 circuit
into a ZX81
|__
ZX80
software - Type in a Space Invaders game into the ZX80
Build your own Jupiter Ace - my page showing
you how to build this old micro
Build your own UK101 - my page showing you how to build
a greatly simplified version of this old micro
Pong - Pictures of
my build of the Atari classic arcade game
My
Machines - My collection of classic 80's micros
To contact me, my current eMail address can be found here. Please note that this address may change to avoid spam.